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What Worked, What Didn’t In 2019

Release Date:2019-12-20


The year started out shaky, but EDA racked up solid growth and semiconductors show good promise for 2020.

DECEMBER 19TH, 2019 - BY: BRIAN BAILEY


2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year.

A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, and some may be entering a trough of disillusionment. But there are increasing numbers of design starts, which account for strong EDA growth, many of them coming from companies that have not designed hardware in the past. And despite some fluctuations, expectations remain high among analysts, who are projecting anywhere from 8% to 12% CAGR over the next five years.


Fig 1. Quarterly EDA, SIP and services revenue by category, Q1 1996 to Q2 2019. Source: ESD Alliance Market Statistics Service

Leading the charge is AI. “Big data and AI applications, including machine learning and deep learning, are now key drivers for the electronics industry,” says Rob van Blommestein, head of marketing at OneSpin Solutions. “This has led to the emergence of heterogeneous computing platforms, both traditional SoCs with embedded FPGA fabric and massive FPGAs that qualify as SoCs, too. Xilinx’s 7nm Versal adaptive compute acceleration platform (ACAP) is a good example of this trend.”

Other markets have been in decline. “The bitcoin SoC market did spiral down drastically as predicted,” says Tom Wong, director of marketing, design IP at Cadence. “Interestingly, the bitcoin SoC players in China have pivoted to artificial intelligence (AI) acceleration SoCs. This will not have meaningful wafer consumption because everything in AI acceleration SoCs is a work in progress without particularly high volume, meaning less than 100 million chips per design. There are many AI acceleration SoC startups in the United States that are in development mode without appreciable wafer consumption yet.”

Luckily, the mobile industry somewhat came to the rescue. “The decline in bitcoin does not produce any surplus wafer capacity as the freed-up capacity is consumed by the resurgence of iPhone unit sales and explosive growth of Huawei phones in China,” adds Wong. “Smartphone sales consumed all the advanced process wafers, and foundries must commit extra CapEx in 2019/2H to ramp further volume to support the demand. Trade disputes between the U.S. and China also distort the supply/demand curves for wafer production and CapEx investment.”

So far, the trade war with China does not seem to be slowing EDA down. Walden Rhines, CEO emeritus of Mentor, a Siemens Business, noted that 2019 Q2 “probably precedes some of the [trade war] actions, but we came off a very strong quarter last quarter and we’re looking at 6.5% this quarter. That’s very strong, and if you look at where the strength is, the Pacific Rim is really the strongest part of the world.”

Some of the new technologies are pressuring the development of the most advanced manufacturing nodes. “We are seeing an accelerated pace of design starts toward advanced nodes below 10nm feature sizes, driven by a huge need for data processing,” says Vic Kulkarni, vice president and chief strategist for ANSYS. “This significant rise in computing power is being driven by the rapid adoption of cloud computing in several verticals, including HPC, 5G, AI, automotive and advanced mobile.”

There is little disagreement about the drivers. “AI, 5G, autonomous cars, Internet of Things (IoT) have been among the major growth drivers in 2019 for the semiconductor industry,” says Casper van Oosten, business field head and managing director for Intermolecular. “These drivers also have increased the complexity of technology and have required greater focus on efficient R&D and data-analysis to identify the right material and integration solutions in order to remain innovative and competitive. Being able to operate in this increasingly data-driven society has brought a year of significant changes with unexpected speed to our company, as well as our customers.”

Intermolecular was acquired by Merck KGaA in 2019, a year marked by continuing acquisitions. M&A activity in the industry totaled about $29 billion, according to IC Insights.

“There were a significant number of mergers and acquisitions (or shedding businesses) within our top-tier semiconductor customers, including Mellanox-NVIDIA, Mobileye-Intel, Renesas-IDT, InPhi-eSilicon, and so on,” says ANSYS’ Kulkarni. “Intel also sold its cell phone modem business to Apple, Marvell announced its intention to sell off its WiFi connectivity segment to NXP and acquire GlobalFoundries’ ASIC business.”

In fact, just in the last week several other sizable deals have been announced.

“Although the pace of M&A was a bit of a surprise for the industry at the outset, we are very excited about the opportunities ahead for the entire ecosystem since these acquisitions indicate significant growth in multiple high-growth verticals, such as automotive, 5G, and HPC,” Kulkarni says. “This will bring multiple technologies and R&D teams together in the merged companies to solve complex system-level issues. According to IC Insights, 2019 is positioned to surpass 2017 as the third largest year for semiconductor M&A.”

Late in 2018, the Electronic System Design Alliance (ESDA) joined forces with SEMI. The goal was to integrate the design segment to its electronics manufacturing supply chain scope, connecting the full ecosystem. “It became clear in 2019 that while design and manufacturing are integral parts of the global electronic product market and supply chain, they are still worlds apart,” says Bob Smith, executive director of the ESD Alliance. “While there is a degree of cooperation and collaboration, each pursues different objectives and has unique challenges. They share many common industry issues and bottlenecks that could be addressed via more extensive collaboration and partnering.”

Technology drivers
While development of the newest nodes continues, they are unable to keep up with the demand for more transistors needed for applications like AI. Part of the problem is that these chips are hitting the reticle limit, and this is causing them to look towards other solutions.

“As predicted, we witnessed the beginning of the 3D-IC explosion,” says John Park, product management group director for IC packaging and cross-platform solutions at Cadence. “Virtually every medium to large semiconductor design company is considering multi-chip(let) 3D-IC alternatives to a single monolithic chip. Moreover, the two large semiconductor fabs both announced 3D-IC reference flows in 2019. The age of More Than Moore is here.”

It has been a long time coming. “This was a pleasant inflection point for us in 2019,” says Kulkarni. “We have been working on package modeling, power and signal integrity, thermal and reliability simulation solution over 10+ years from monolithic IC package, PGA (pin grid array), surface-mount, SiP, 2.5D to 3D stacked die packaging. We have now accelerated certification of our solutions for packaging with TSMC and MDI (multi-die integration) with Samsung.”

This creates a new opportunity for EDA. “New tools are required with the multi-chip(let) 3D approach to plan and manage the top-level connectivity and export design/packaging alternatives,” says Park. “This top-level planning and management solution is now part of all multi-chip(let) reference flows. Today this approach typically extends to the process of chip interface planning and package I/O optimization without much consideration for the PCB. Expect to see this change in the next couple of years as architects and designers will need to plan and optimize the complete chip(let)s, package and PCB system.”

FPGAs also continued on their growth trajectory, driven in large part by the need for flexibility in new markets such as AI, automotive and 5G, where algorithms, standards and interfaces continue to change at a rapid pace. Being able to program hardware to accommodate those changes is critical, but it isn’t as simple as it sounds, which in turn has fueled high-level synthesis growth.

“The FPGA benefits in performance and flexibility for AI applications are well understood. The programming model has been the most significant challenge,” said Jordon Inkeles, vice president of product at Silexica. “The challenges in programming models won’t be solved by a single flow. It will be solved by a combination of flows that match the expertise of the developer. HLS extracts away the hardware to enable software engineers to be successful, but that’s only recently with tools like SLX FPGA from Silexica. Prior, most HLS users were still hardware engineers. HLS will provide the flexibility needed to take advantage of the FPGA for the software developer. However, TensorFlow and Caffe will still sit at a higher level of abstraction utilizing ML frameworks and libraries for data scientists to accelerate their algorithms.”

Interfaces
Interfaces used to be considered a dull necessity, but recently they have become the enablers for new capabilities. “As predicted last year, the global 5G rollout has been gathering momentum and will continue throughout 2020,” says Paul Williamson, vice president and general manager for the Client Line of Business at 
Arm. “The Tokyo Olympics will be where the possibilities enabled by 5G are showcased to a global audience of billions. This will mark the start of the ‘5G era’ where new and improved use-cases and experiences will accelerate on devices.”

Wired connectivity is not standing still either. “The USB industry standard evolved once again as the USB4 specification was released by the USB Implementers Forum,” says Amin Shokrollahi, CEO for Kandou. “This offers faster connections for video processing and data transfer over a USB-C connector. It also holds the promise of a way for differing signal conditioning technologies to address system challenges of high-speed signals.”

Market drivers
It is difficult to ignore the meteoric rise in AI and the new applications it is driving in almost every segment of the industry. “The uptick of system companies designing bespoke silicon is transforming the industry,” says Kulkarni. “System companies like Google, Amazon, Facebook, Microsoft, and others announced plans to build their own AI chips at a much faster rate. It was encouraging to see the emergence of standardization efforts under the ODSA-defined open interface (Open Domain-Specific Architectures), which will help reduce the complexity and cost of designing high-performance accelerators built from the best-of-breed chiplets.”

This trend is not just happening in AI. “We saw conventional automotive OEMs like Tesla, Toyota (with Denso collaboration) and others starting R&D in designing bespoke silicon chips (or chiplets-based designs) instead of going through the conventional Tier 1 suppliers,” adds Kulkarni. “The automotive segment has become the new battleground for semiconductor industry.”

The rise in automotive has also created a demand for new EDA tools. “The increasing importance of functional safety is clear by the amount of attention being paid to the ISO 26262 standard for automotive electronics,” says OneSpin’s van Blommestein. “Autonomous vehicles clearly set a high bar for safety, as well as security and trust, but we are seeing the need in other areas as well. Nuclear power plants, avionics, military systems, and implantable medical devices are all applications where there is little or no margin for error. Developers need to formally prove that their designs are safe, secure, and trustworthy.”

Not all of the news from automotive is positive. “2019 was the year when many people started to realize that the dream of autonomous cars on our roads is still a long way out,” says Michiel Ligthart, chief operating officer for Verific Design Automation. “Let’s be honest, what good is a technology that requires me to have my hands (sweaty palms and all) on the wheel and my foot near the brake so I can take over at any moment when the robot fails?”

Other technology areas are also struggling to overcome adoption resistance. “While we are still in the early days of immersive experiences on mobile devices, I’ve seen positive signs that dedicated XR devices will provide the performance and untethered experience needed to ensure future success,” says Arm’s Williamson. “One current example is the Oculus Quest, which is providing the untethered VR gaming experience consumers have been craving for years. While we’re at the beginning of AR growth, the AR productivity benefits for industry have already come to the fore, as highlighted through the Microsoft HoloLens 2. This will continue to advance in 2020.”

RISC-V
The rise of the RISC-V ISA continues unabated. “We predicted that RISC-V would become a major factor in SoC development, and that a large ecosystem would arise to support this architecture,” says van Blommestein. “This has certainly been the case. There are a plethora of open-source and commercial processor cores available, along with software, EDA tools, and other supporting technology. The RISC-V Foundation now has more than 325 members companies and organizations. It’s more a question of who isn’t working with RISC-V than who has adopted it.”

Others agree. “We see a lot of horizontal applications for RISC-V,” said Jerry Ardizzone, vice president of worldwide sales at Codasip. “There is a lot of activity in AI right now. People want to lay down a lot of processors and maybe do a little customization of the processor itself, and repeat that many times. So there’s quite a bit of interest. But over time you’re going to see this in all markets. This is not going to happen immediately. In the next few years, as the companies that provide processor IP and third-party ecosystem around it get bigger and develop more IP, you will see us moving to a broad number of market spaces.”

Put simply, there’s more to building an ISA than a spec. It requires a full ecosystem and a tools and security infrastructure, and all of that takes time. Nevertheless, much of the initial groundwork began taking form in 2019.

“We are trying to identify the top challenges in security for our RISC-V community,” said Helena Handschuh, a Rambus fellow who chairs the security standing committee for the RISC-V Foundation. She pointed to micro-architectural security implementation flaws, security certification and assurance, post-quantum crypto, and how to best disclose security vulnerabilities as the top concerns. “There are many opportunities, and it’s a really, really big ecosystem. But the security question in that world is quite a challenging one, and we’re working on it.”

Tool developments
In addition to the tool development opportunities already noted, other areas are growing in importance. “We are seeing very strong adoption of static signoff,” says Prakash Narain, president and CEO for Real Intent. “At DAC this year, several users presented their best practices for static signoff. A key recommendation was that not only is static signoff starting to get accepted as a different approach to the verification problem — different from simulation, different from formal — it is its own approach and hence requires appropriate product design.”

We are seeing increased usage of FPGAs, either standalone or embedded. “We noted that formal equivalence checking for FPGA designs had become a key technology to establish trust in the development chain, and we predicted significant growth in 2019,” says van Blommestein. “The technology can ensure that no hardware Trojans have been introduced during the development process. In addition, FPGA tools for synthesis and place-and-route are continually adding aggressive optimizations that must be verified formally. Usage of FPGA equivalence checking is expanding for both reasons.



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