NXP to Jump to TSMC’s 5nm for Next-Gen Auto SoC Platform
NXP Semiconductors announced Friday that it will become the first automotive chip company to jump to TSMC’s 5nm process technology for the next generation “high-performance safe compute” automotive platform. NXP and TSMC expect to deliver the first sample devices to NXP’s key customers toward the fall of 2021.
As “massively parallel innovations” happen in the automotive industry, car OEMs must deal with “exploding software, tremendously expensive bill of materials and improved safety” in their vehicle architecture, Henri Ardevol, executive vice president and general manager, Automotive Processing at NXP, told EE Times. With the new automotive processing platform built on N5P, an enhanced version of TSMC’s 5nm technology, NXP hopes to move OEMs’ “socket-by-socket” discussion to that of “entire vehicles.”
Perhaps, with this announcement, NXP is indicating that it will leapfrog competitors using 7nm, said Kevin Krewell, principal analyst at Tirias Research. “To me,” said Krewell, NXP’s message is that it is “in the automotive game to win it.”
Regardless of the process node, industry observers remain a little baffled about what exactly NXP’s new platform would look like. Krewell, for one, believes NXP “definitely needs to enhance its architectural offerings to compete with MobileEye, Qualcomm, Nvidia, Renesas, etc.”
Mike Demler, senior analyst at The Linley Group, pointed out that while this is interesting news, “NXP’s automotive platform is very broad, and 5nm technology isn’t appropriate for all of it.”
Indeed, NXP’s MCU and MPU portfolio is large, Ardevol acknowledged. It ranges from general purpose microcontrollers used for body and chassis controls, to i.MX microprocessors for infotainment units and automotive domain controllers. NXP has also used diverse processing technologies, ranging from 90nm process for MCUs with embedded non-volatile memory, 28-nm FD-SOI process used in i.MX application processors to 16nm FinFET-based procesoors.
NXP’s goal is to “harmonize software infrastructure” by offering a consistent core architecture that can be used “across domains,” noted Ardevol. What NXP is not promising is a super-duper brute-force high performance computing platform that would be hard to scale up or down or difficult to be deployed in a vehicle in a modular fashion.
Safety first NXP will put safety at the heart of the architecture, said Ardevol. Today, the automotive industry has “high performance compute” and “safe compute” platforms, he noted. For ADAS and AV, vehicle OEMs often build parallel systems. One follows the main path with low-integrity functionality, while another layer is added for safety processing. System designers also incorporate a safety checker in a vehicle, with another processor put in place to calculate the escape path for emergencies. All told, “This is a system that’s very hard to scale down, and it is still very expensive,” noted Ardevol.
As an example, Ardevol referred to an AV architecture BMW recently unveiled. The last time EE Times talked to BMW, the German carmaker told us that for Level 3 models, it is adding two Mobileye EyeQ56 , two Intel Denverton CPUs and another Aurix. For Level 4/5 vehicles, BMW expands the configuration to three EyeQ5, one Xeon 24C and Aurix. BMW is seeking to achieve safety by design by implementing a doer-checker approach.
While NXP maintains similar design goals for its next-generation automotive compute platform, Ardevol observed that an AV system architecture like the one unveiled by BMW would still remain expensive.
Noting that the tremendous complexity is growing on the software level, Ardevol said, “We need to design the parallel systems [explained above] into the fabric of a new SoC.” Meanwhile, NXP is designing a new core architecture that works well across domains on a system level. The mission for the new platform is “to facilitate reducing the complexity and bringing down the cost,” he summed up.
Leapfrogging competition Ardevol confirmed that NXP is the first among automotive semiconductor companies to go for 5nm process technology.
For NXP, which has worked with TSMC since the days of Philips Semiconductors, jumping to 5nm with TSMC “was an easy decision,” said Ardevol. “The investment that is required to go to 7nm or 5nm is similar.” With 5nm technology, NXP can achieve high levels of integration while lowering power consumption.
However, the engineering work to get the 5nm process qualified for automotive-grade and functional safety “takes a lot of paperwork and documentation. It also needs to be qualified to reliability level above consumer devices,” observed Krewell.
With samples scheduled for delivery in 2021, Ardevol acknowledged that over the last few months, TSMC and NXP have been “engaged with the 5nm, ‘auto-grade’ ecosystem players” including IP suppliers, tool vendors and others providing design enablement, said Ardevol, “as one team.” Engineering work, already started, is “collaborative” because advanced process nodes need more co-design.
Asked where NXP’s competitors stand in terms of process technologies, Demler said, “I don’t know of any other automotive processors targeting 5nm technology.”
Demler expects Nvidia’s Orin to use 7nm. He said that Mobileye’s EyeQ5 is built on 7nm, but EyeQ6 could move to 5nm. Demler added, “An interesting point here is that Mobileye uses STMicroelectronics for its chip design. The earlier EyeQ processors used ST’s manufacturing process, but the newer ones use TSMC. ST worked with TSMC to develop the automotive process that EyeQ uses, so it’s interesting to see NXP jumping into that position for 5nm.”
The first product on 5nm The first product to go on 5nm will be an eCockpit SoC followed by others based on NXP’s S32. For example, S32G, designed for a gateway processor by combining an automotive microprocessor and an enterprise network processor will be a good step for NXP’s customers to use high-performance, robust ADAS built on 5nm.
But NXP’s endgame is designing a consistent architectural core that can be used in a modular manner across distributed domains — ranging from gateway processors, cockpit to sensor fusion, path planning and decision-making processors. Depending on where the processor will be used, different AI accelerators can be added, added Ardevol.
Instead of simply playing the game of bigger and faster DMIPS, TOPS and TFLOPS, “our goal is to build a high-performance safe compute platform — integrated with functional safety and lock-step operations,” explained Ardevol. NXP is not asking its customers to go 180. “This will be a phased approach. We hope this will allow OEMs to have a meaningful roadmap, enabling them to simplify their software development and designing in safety.”
The Linley Group’s Demler concluded: “This announcement is important to NXP as a statement that it wants to be among the technology leaders.” However, he cautioned, “Don’t expect to see such a chip [based on the brand-new architecture] right away.” To start production for such chips will take at least two years, if not longer, he said.
On the other hand, networking chips and other automotive processors mentioned by NXP are more likely to sample in 2021, he added.
Author: Junko Yoshida
Former beat reporter, bureau chief, and editor in chief of EE Times, Junko Yoshida now spends a lot of her time covering the global electronics industry with a particular focus on China. Her beat has always been emerging technologies and business models that enable a new generation of consumer electronics. She is now adding the coverage of Chinaâ€™s semiconductor manufacturers, writing about machinations of fabs and fabless manufacturers. In addition, she covers automotive, Internet of Things, and wireless/networking for EE Times' Designlines. She has been writing for EE Times since 1990.